In digital telecommunications systems, digital signal streams are transported at a variety of rates, synchronously or asynchronously, and in all cases, clocks are used for processing these digital signal streams. These clocks must be brought into synchrony for proper data exchange and timing information of some form is transported from the source to destination. Digital signal streams are also frequently regenerated at a proper rate as they experience signal deterioration by noise, delays, jitter etc. They are also multiplexed to produce higher bit rates for higher capacity transmission systems, as a means of utilizing the same transmission medium economically for many different users. In multiplexing, there are more than one digital transmission hierarchies for telecommunications for different parts of the world. FIG. 1 shows one example of digital hierarchies used in North America. In the Figure, four DS1 signal streams are multiplexed into one DS2 signal stream and 7 DS2 signal streams are then multiplexed into a DS3 signal stream. The bit rates of levels are also shown in the Figure. A major problem of multiplexing involves synchronizing the input signal streams. Digital signal streams cannot be directly interleaved and guaranteed their subsequent identification unless the pulse rates of all the signal sources are locked to a common clock. This means that all the signal streams are frequency synchronous, or else they are asynchronous and brought into frequency synchronism by the multiplexer. The multiplexer system can establish frequency synchronism by increasing the bit rate of each separate input to one common rate before combining them into one bit stream. This adds extra time slots into which extra pulses can be stuffed. In pulse stuffing, all incoming digital signal streams are stuffed with a sufficient number of pulses to raise each of their rates to that of the desired common rate. In demultiplexing, a single signal stream of a high rate is split into a plurality of signal streams. Each of the split signal streams is stripped of stuffed bits which are so identified and is desynchronized into a single signal stream of a lower rate according to the common clock.
By referring to FIG. 2, this rate adjustment can be explained in more detail. For example, FIG. 2 shows the structure of a DS2 signal stream which consists of 1176 bits in a frame called M-frame which is made up of 4 subframes, each of 294 bits. Each subframe includes a stuff block in which one specific bit position is reserved for stuffing. This position is used for stuffing a null bit if stuffing is required or it can be used for data bit if no stuffing is required. Therefore, when the stuff position is used for data, there are 6.times.48=288 bits of DS1 data in a DS2 M frame. When a null bit is put in the stuff position, there are 287 bits of DS1 data per DS2 frame. Therefore, the DS1 data rate can be adjusted by changing how often the stuff position is used for null bit or data bit. The range of adjustment therefore is from 6.312.times.287/1176=1.5404 Mb/s to 6.312.times.288/1176=1.5458 Mb/s.
FIG. 3 shows the structure of DS3 signal stream. A DS3 stream consists 4,760 in an M-frame which is made up of 7 subframes, each of 680 bits. The stuff position in each subframe is also arranged in a similar fashion as in DS2 stream. Therefore in a DS3 stream, there are 7 stuff positions in one M-frame, one per DS2.
It should be noted that although DS streams are described in detail above, essentially similar digital signal hierarchies are used in Europe and elsewhere such as E1, E2, and E3. The number of bits in a frame, specific bit assignments etc. may be different among them but the concept of the invention is equally applicable to any of these digital signal streams.
A broadband network such as SONET handles ATM traffic in addition to other synchronous traffic. While a network is synchronous in operation, ATM traffic is asynchronous in nature and thus such a data stream experiences the cell jitter, cell delay variation and other fluctuations as it moves through the network toward a destination node. Even when an ATM network is transporting a CBR (constant bit rate) stream between a source node and a destination node, the clock frequency at the destination node cannot be traced directly back to that of the source node by the regular, periodic arrival of the CBR stream. A few techniques have been used to convey the difference between the network clock frequency and the service clock frequency (frequency of the data being transported). U.S. Pat. No. 5,260,978 Nov. 9, 1993 Fleischer et al describes a technique called SRTS (Synchronous Residual Time Stamp) for timing recovery in a broadband network. The patent shows that only a small number of overhead bits (called P bits) are required to express unambiguously the variation from a nominal value of the difference between the two clock frequencies. The P bits are called SRTS bits. The resolution is governed by the nominal value of the frequency difference and the clock tolerance, and determines the required minimum number of P-bits. Under normally expected parameters, the number of these P-bits would be significantly smaller than the number of bits that would be required to express the clock frequencies, e.g. 3 bits instead of 13 bits. A typical sampling period is 3008 which corresponds to a period of 8 ATM cells and a 47 octet payload per cell.
The SRTS method described in the above-referenced patent makes use of phase locked loops (PLLs) to generate an analog clock signal derived from the SRTS values. U.S. Pat. No. 5,608,731 Mar. 4, 1997 Upp et al, on the other hand, describes a digital closed loop clock recovery for SRTS. In the patent, 4 bits are used for SRTS to recover clock pulses of a DS1 signal stream.
FIG. 4 illustrates a functional block diagram in the Tx direction of a typical DS1/DS2 multiplexer (often called M12 multiplexer). As mentioned earlier, in the multiplexer, before combining the lower rate signal streams, the service clock of each lower rate signal stream must be recovered in relation to the network reference clock and then each lower rate signal must be rate adjusted to be synchronous with each other by appropriate stuffing. Therefore in FIG. 4, ATM cells from the network are buffered at buffer 30 and a DS1 signal stream is fed to a FIFO 32. Meanwhile, SRTS values are captured from the ATM cell stream. They are then processed at 34 by referring to the network reference clock, e.g., 2.430 MHz and a DS1 clock is regenerated through PLL 36. At FIFO, the incoming DS1 signal stream is written in in response to the regenerated DS1 clock. On the other hand, DS1 signal stream stored in the FIFO are read out and sent to DS2 mapper 38 in accordance with the clock signal obtained from DS2 clock 40. Whenever the FIFO reaches a certain threshold of fullness, the DS2 mapper will stuff in DS1 data into the stuff position. When this happens the rate at which the FIFO is emptied increases and eventually the fullness of the FIFO will drop below a threshold 42 and the DS2 mapper will then put nulls into the stuff position. Having adjusted each DS1 signal stream into alignment with each other by proper stuffing, DS2 mapper maps four DS1 signal streams into a DS2 signal stream.
FIG. 5 illustrates a functional block diagram in the Rx direction of a known M12 multiplexer. A DS2 signal stream 50 is disassembled at a disassembler 52 to DS1 signal streams, each DS1 signal stream properly destuffed. Each DS1 signal stream is sent and stored in FIFO 54 according to write clock derived from DS2 clock 56. Each DS1 stream is read out from the FIFO according to a regenerated clock for the respective DS1 stream. The respective clock is regenerated from the data bits coming out of the disassembler and the stuff/don't stuff signal through a PLL 58. The data is read out of the FIFO in accordance with this recovered clock and stored in the ATM cell buffer 60. SRTS values are calculated at 62 with respect to the network reference clock and inserted into the appropriate places in the ATM cells as they are sent to the ATM network.
While an M12 multiplexer is described above, in actual practice it is more common that DS1 signal streams are multiplexed into a DS3 signal stream at the same location. As shown in FIG. 6, this is performed by a series of M12 and M23 multiplexing. In the Figure, seven M12, each with an appropriate stuffing operation at 66 are combined to generate a DS3 signal stream. Some stuffing determination based on various means is performed here.
When 28 DS1 signal streams are multiplexed to or demultiplexed from a DS3 signal stream, the range of difference in DS1 clock frequencies among all DS1 signal streams is greater than it would be when only one DS1 signal stream is regenerated as done in the above prior art SRTS techniques, producing wider swings in SRTS values.
The SRTS clock recovery techniques discussed above deal mainly with regenerating a digital signal e.g. DS1 signal which is already fairly narrowly bounded. These techniques therefore do not have a sufficient dynamic range to deal with multiplexing and demultiplexing of DS1 and DS3 streams.
The multiplexer/demultiplexer of the invention makes use of the SRTS technique but it is entirely digital in operation. It also handles digital signal streams of wider hierarchies, such as signals spanning between DS1 and DS3. As the operation is entirely digital, the technique of context switching can also be applied to it. In one embodiment, the contents of the various registers that make up the inventive algorithm are stored in a memory for each of the 28 DS1 signal streams. As each DS1 signal stream is processed, the values for the registers are loaded from the memory, the registers are updated appropriately, and the new values stored back into memory. By making the algorithm completely digital, one avoids an analog PLL, the device pins that it needs, as well as any external components that a PLL may require for each of the 28 DS1 signal stream. Furthermore, context switching allows a single set of hardware registers along with a memory to replace 28 sets of the DS1 hardware registers which would be required for the prior art techniques mentioned above. It is therefore possible to achieve significantly higher levels of integration.
A copending application Ser. No. 08/659,395 filed on Jun. 6, 1996, inventors Coady et al describes in detail the invention relating to context switching of a plurality of digital signal streams.